september 2006 advance information copyright ? alliance memory. all rights reserved. as7c31025c 3.3v 128k x 8 cmos sram (center power and ground) 9/20/06, v. 1.0 alliance memory p. 1 of 9 ? features ? industrial and commercial temperatures ? organization: 131,072 x 8 bits ? high speed - 10 ns address access time - 5 ns output enable access time ? low power consumption via ship deselect ? easy memory expansion with ce , oe inputs ? center power and ground ? ttl/lvttl-compatible , three-state i/o ? jedec-standard packages - 32-pin, 300 mil soj - 32-pin, 400 mil soj - 32-pin, tsop 2 ? esd protection 2000 volts logic block diagram 131,072 x 8 array (1,048,576) sense amp input buffer a10 a11 a12 a13 a14 a15 a16 i/o0 i/o7 oe ce we address decoder address decoder control circuit a9 a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 a15 a14 a13 oe i/o7 i/o6 gnd v cc i/o5 i/o4 a12 a11 a10 a9 a8 a0 a1 a2 a3 ce i/o0 i/o1 v cc gnd i/o2 i/o3 we a4 a5 a6 a7 as7c31025c 32-pin soj (300 mil) 32-pin soj (400 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 v cc gnd i/o2 i/o3 we a16 a15 a14 a13 oe i/o7 i/o6 gnd v cc i/o5 i/o4 a9 a8 a4 a5 a6 a7 a12 a11 a10 32-pin tsop 2 as7c31025c
as7c31025c 9/20/06, v. 1.0 alliance memory p. 2 of 9 ? functional description the as7c31025c is 3v a high-performance cmos 1,048,576-bit static random access memory (sram) device organized as 131,072 x 8 bits. it is designed for memo ry applications where fast data access, low power, and si mple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10 ns with output enable access times (t oe ) of 5 ns are ideal for high-performance applications. the chip enable input ce permits easy memory and expansion with multiple-bank memory systems. when ce is high the device enters standby mode. a write cycle is accomplish ed by asserting write enable ( we ) and chip enable ( ce ). data on the input pins i/o0 through i/o7 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins onl y after outputs have been disabled with output enable ( oe ) or write enable ( we ). a read cycle is accomplished by asserting output enable ( oe ) and chip enable ( ce ), with write enable ( we ) high. the chip drives i/o pins with the data word referenced by the input a ddress. when either chip enable or output en able is inactive or write enable is act ive, output drivers stay in hi gh-impedance mode. all chip inputs and outputs are ttl-compat ible, and operation is from a single 3.3 v supply. the as7c31025c is packaged in comm on industry standard packages. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or any other conditions ou tside those indicated in the oper ational sections of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = don?t care, l = low, h = high. parameter symbol min max unit voltage on v cc relative to gnd v t1 ?0.50 +4.6 v voltage on any pin relative to gnd v t2 ?0.50 v cc + 0.5 v power dissipation p d ?1.25w storage temperature (plastic) t stg ?55 +125 o c ambient temperature with v cc applied t bias ?55 +125 o c dc current into outputs (low) i out ?50ma ce we oe data mode h x x high z standby (i sb , i sb1 ) l h h high z output disable (i cc ) lhl d out read (i cc ) llx d in write (i cc )
as7c31025c 9/20/06, v. 1.0 alliance memory p. 3 of 9 ? recommended operating conditions v il min = ?2.0v for pulse width less than 5ns, once per cycle. v ih min = ?v cc + 2.0v for pulse width less than 5ns, once per cycle. dc operating characteristics (over the operating range) 1 capacitance ( f = 1 mhz, t a = 25 o c, v cc = nominal ) 2 parameter symbol min nominal max unit supply voltage v cc 3.0 3.3 3.6 v input voltage v ih 2.0 ? v cc + 0.3 v v il ?0.5 ? 0.8 v ambient operating temp erature (industrial) t a ?40 ? 85 o c parameter sym test conditions as7c31025c-10 unit min max input leakage current | i li | v cc = max, v in = gnd to v cc ?5 a output leakage current | i lo | v cc = max, ce = v ih , v out = gnd to v cc ?5 a operating power supply current i cc v cc = max ce v il , f = f max , i out = 0 ma ? 150 ma standby power supply current 1 i sb v cc = max ce v ih , f = f max ?50 ma i sb1 v cc = max, ce v cc ?0.2 v, v in 0.2 v or v in v cc ?0.2 v, f = 0 ? 10 ma output voltage v ol i ol = 8 ma, v cc = min ?0.4v v oh i oh = ?4 ma, v cc = min 2.4 ? v parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe v in = 3dv 6 pf i/o capacitance c i/o i/o v out = 3dv 7 pf note: 1. this parameter is guaranteed by device characterization, but is not production tested.
as7c31025c 9/20/06, v. 1.0 alliance memory p. 4 of 9 ? read cycle (over the operating range) 3,9 key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (ce and oe controlled) 3,6,8,9 parameter symbol as7c31025c-10 unit notes min max read cycle time t rc 10 ? ns address access time t aa ?10ns3 chip enable ( ce ) access time t ace ?10ns3 output enable ( oe ) access time t oe ?5ns output hold from address change t oh 4?ns5 ce low t o output in low z t clz 4 ? ns 4, 5 ce high to output in high z t chz 0 5 ns 4, 5 oe low to output in low z t olz 0 ? ns 4, 5 oe high to output in high z t ohz 0 5 ns 4, 5 power up time t pu 0 ? ns 4, 5 power down time t pd ?10ns4, 5 undefined/don?t care falling input rising input address d out data valid t oh t aa t rc current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% data valid t rc1 ce t ohz
as7c31025c 9/20/06, v. 1.0 alliance memory p. 5 of 9 ? write cycle (over the operating range) 11 write waveform 1 (we controlled) 10,11 write waveform 2 (ce controlled) 10,11 parameter symbol as7c31025c-10 unit notes min max write cycle time t wc 10 ? ns chip enable ( ce ) to write end t cw 7?ns address setup to write end t aw 7?ns address setup time t as 0?ns write pulse width t wp 7?ns write recovery time t wr 0?ns address hold from end of write t ah 0?ns data valid to write end t dw 5?ns data hold time t dh 0 ? ns 4, 5 write enable to output in high z t wz 0 5 ns 4, 5 output active fr om write end t ow 3 ? ns 4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr t aw address ce we d out t cw t wp t dw t dh t ah t wz t wc t as data valid d in t wr
as7c31025c 9/20/06, v. 1.0 alliance memory p. 6 of 9 ? ac test conditions notes 1 during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a and b. 4t clz and t chz are specified with cl = 5 pf, as in figure b. transition is measured 200 mv from steady-state voltage. 5 this parameter is guaran teed, but not 100% tested. 6 we is high for read cycle. 7 ce and oe are low for read cycle. 8 address is valid prior to or coincident with ce transition low. 9 all read cycle timings are referen ced from the last valid address to the first transitioning address. 10 n/a 11 all write cycle timings are referenced from the la st valid address to the first transitioning address. 12 n/a. 13 c = 30 pf, except all high z and low z parameters where c = 5 pf. 255 ? output load: see figure b. ? input pulse level: gnd to 3.0 v. see figure a. ? input rise and fall times: 3 ns. see figure a. ? input and output timing reference levels: 1.5 v. c 13 320 d out gnd +3.3 v 168 thevenin equivalent: d out +1.728 v figure b: 3.3 v output load 10% 90% 10% 90% gnd +3.0 v figure a: input pulse 3 ns
as7c31025c 9/20/06, v. 1.0 alliance memory p. 7 of 9 ? package dimensions 32-pin tsop 2 nn/2+1 1n/2 d e1 e l a c zd c b a1 a seating plane e d e1 pin 1 b b a1 a2 c e seating plane e2 a 32-pin soj 300 mil/400 mil symbol 32-pin tsop 2 (mm) min max a ?1.20 a1 0.05 0.15 b 0.3 0.52 c 0.12 0.21 d 20.82 21.08 e1 10.03 10.29 e 11.56 11.96 e 1.27 bsc l 0.40 0.60 zd 0.95 ref. 0 5 symbol 32-pin soj 300 mil 32-pin soj 400 mil min max min max a 0.128 0.145 0.132 0.146 a1 0.025 - 0.025 - a2 0.095 0.105 0.105 0.115 b 0.026 0.032 0.026 0.032 b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013 d 0.820 0.830 0.820 0.830 e 0.255 0.275 0.354 0.378 e1 0.295 0.305 0.395 0.405 e2 0.330 0.340 0.435 0.445 e 0.050 bsc 0.050 bsc
as7c31025c 9/20/06, v. 1.0 alliance memory p. 8 of 9 ? ordering codes part numbering system package volt/temperature 10 ns 300-mil soj 5v industrial as7c31025c-10tjin 400-mil soj 5v industrial AS7C31025C-10JIN tsop 2 5v industrial as7c31025c-10tin as7c x 1025b ?xx x x x sram prefix voltage: 3 = 3.3 v cmos device number access time package: tj = soj 300 mil j = soj 400 mil t = tsop2 temperature range i = industrial, -40 c to 85 c n = lead free part
alliance memory, inc. 1116 south amphlett san mateo, ca 94402 tel: 650-525-3737 fax: 650-525-0449 www.alliancememory.com copyright ? alliance momory all rights reserved part number: as7c31025c document version: v. 1.0 ? copyright 2003 alliance memory, inc. all ri ghts reserved. our three-poi nt logo, our name and inte lliwatt are trademarks or re gistered trademarks of alliance. all other brand and product names may be the trademarks of th eir respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at th e time of issuance. alliance re serves the right to chang e or correct this data at any time, without notice. if the product described herein is under de velopment, significant changes to these specifications are pos sible. the information in this product data sheet is inte nded to be general descriptive information for po tential customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to a ny user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warr anties related to the sale and/or use of alliance products i ncluding liability or warranties related to fitness for a particul ar purpose, merchantability, or infringement of any inte llectual property rights, e xcept as express agreed to in alliance's terms and conditions of sale (whi ch are available from alliance). all sale s of alliance products are made exclusivel y according to alliance's terms and conditions of sale. th e purchase of products from alliance does not conv ey a license under any patent rights, copyrig hts; mask works rights, trademarks, or any other intellectual proper ty rights of alliance or third parties. alliance does not auth orize its products fo r use as critical components in life-supporting systems where a malfunction or failure may reasonabl y be expected to result in si gnificant injury to the user, and the inclusion of alliance products in such life-su pporting systems imp lies that the manufacturer assumes all risk of such use and agrees to inde mnify alliance against all claims arising from such use. as7c31025c ? ?
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